The present invention relates to methods and apparatus for developing hardware modules that can be used in system level simulations. More specifically, the present invention relates to methods and apparatus for automating the generation of system level simulation hardware modules from Register Transfer Language (RTL) representations of the modules.
Simulink® (available from The MathWorks, Inc. of Natick, Mass.) and similar system level simulators allow users to enter and simulate logic designs representing Digital Signal Processors (DSPs) and other electronic devices. The logic designs are algorithmic representations. Users design DSP algorithms in system level simulators by entering logic blocks and associated connections in a user interface window representing the overall design. The individual logic blocks come with associated code for executing the functions of the blocks. During a system level simulation, the simulator executes the code for each individual block to provide a simulation result; Typically, the code is written in C++ or other appropriate compilable language.
Frequently, the logic blocks used to create hardware designs are available in libraries of pre-created modules. However, these modules are typically limited to algorithm level representations (as opposed to hardware level representations). Thus, they represent logic by function or behavior only, not by hardware operation.
On a somewhat different historical path, many specific hardware modules are available in libraries for electronic design automation. These modules are intended to facilitate hardware design, compilation, simulation, and programming using conventional Electronic Design Automation (EDA) tools such as gate level synthesizers and compilers (e.g., the Quartus® II design tool available from Altera Corporation of San Jose, Calif.). Designs created from such modules can be simulated to give results that accurately predict the performance of the final hardware implementation. But the EDA environments that make use of such modules lack many popular features of system level simulators such as Simulink.
Recently, a few companies have introduced system level simulation products that provide some measure of hardware simulation. These include the “DSP Builder” product from Altera Corporation, the “System Generator for Simulink” available from Xilinx, Inc. of San Jose, Calif., and the “Simulink RTW” tools available from The MathWorks, Inc. These products allow bit and cycle accurate system level simulation of hardware designs. Hence there is a movement toward merging the functionality of conventional system level simulators and conventional EDA tools for hardware development.
While the available hardware modules for EDA tools come in many different forms, they generally include a register transfer level description of the hardware logic for their modules. From this RTL description, the EDA tools, can elaborate, synthesize, simulate, etc. Some of these hardware modules include pre-synthesized gate level logic and even pre-compiled logic.
What most of these modules lack, however, is code for implementing their functions in a system level simulator such as Simulink. Yet, as mentioned, products such as the DSP Builder product from Altera Corporation allow entry of hardware modules in system level simulators. As these products become more widely deployed and available for designing and simulating true hardware (as opposed to merely algorithms for subsequent implementation in hardware), the large base of hardware modules must be provided with simulation code (e.g., C++ code) for execution in system level simulators.
In short, current libraries of hardware modules having appropriate system level simulation representations are severely limited. The large libraries of hardware modules that exist represent hardware only in RTL description (and sometimes in a synthesized, compiled form), but not in a C++ functional description suitable for system level simulation.
Thus, the EDA industry needs some mechanism for providing the large existing base of hardware modules with code for executing their logical or functional operations in system level simulators. Unfortunately, coding appropriate system level representations of hardware modules for system level simulation represents significant additional effort on the part of the module designer. And the problem is not limited to vendors and developers of hardware modules. It extends to individual designers or companies employing designers, who need to conduct a system level simulation but do not have libraries of hardware modules (whether developed in-house or purchased elsewhere) that comprise code for system level simulation. For all of these people and organizations, this remains a significant obstacle to deploying existing hardware modules in system level simulators. Hence the potential of system level simulators for EDA remains unrealized.